Leakage current is a serious problem for deep-submicron CMOS devices. The leakage current of a CMOS device typically can be measured with regard to sub-threshold voltage leakage, junction leakage, gate leakage and gate induced drain leakage currents. Reducing leakage current to lower system power dissipation is presently a challenge in process technology development and circuit innovation.
It is typically difficult to accurately detect or measure very small currents. One method for measuring small leakage currents is to duplicate a large number of devices that each exhibit a very small current leakage so that the accumulation of each of the small leakage currents may amount to a detectable and measurable quantity that is representative of the leakage current of an individual device (i.e., by dividing the total detected current by the number of contributing devices). This approach is used in detecting leakage current in DRAM memories as described below.
A dynamic random access memory (DRAM) memory cell is said to be in an inactive state if its corresponding access transistor is turned “off” by applying voltage VSS or a voltage level VBB lower than VSS on the gate of an n-channel MOS access transistor, or by applying VDD or a voltage level VPP higher than VDD on the gate of a p-channel MOS access transistor. The charge stored in a cell capacitor represents a single bit of information. Unfortunately, the charge stored in the cell capacitor is not held very well when the access transistor is turned off, and it will be gradually lost by leakage current from the access transistor and the capacitor. Therefore, the cells must be refreshed periodically.
As noted, inactive cells exhibit leakage current from the access transistors and dielectric leakage current from the storage capacitors. The leakage current also depends, however, on the information stored in the memory bit cell, i.e., in the storage capacitor; that is, the leakage is different for memory cells holding binary “1” and binary “0”. Normally, the leakage current of a single bit is too small for accurate detection. To measure the leakage current of a DRAM cell a large number of memory bit cells, e.g., several thousand cells, are arranged in a structure and biased, as shown in FIGS. 1a and 1b with regard to n-channel and p-channel transistors, respectively. With regard to the monitoring array 100 of FIG. 1a, each dummy memory cell includes an n-channel transistor 110 and a corresponding storage capacitor 135 (labeled Cs). The transistor 110 can be applied a proper bias voltage on its gate to turn “on” or turn “off” the connection between the capacitor and the bit line. N-channel transistors 110 are electrically connected in parallel at corresponding source nodes 112 by a common bit line 120, which may be set to a voltage referred to as VBL. The gate node 114 of each transistor 110 is connected to a common word line 125, which may be set to a voltage referred to as VSSB sufficient to turn transistors 110 off. Each drain node 116 of each transistor 110 is further connected to a substantially similar capacitor 135, each of which is connected to a common voltage plate 140. Common voltage plate 140 has a voltage, referred to as VCP, applied thereto. The drain node 116 of each transistor 110 is further electrically connected to a common extraction node 130 that allows for the measurement of an accumulated leakage from all coupled transistors 110 and capacitors 135.
As noted above, FIG. 1B illustrates a prior art monitoring circuit 101 comprising cells including p-channel transistors 111 and storage capacitors Cs 135. The biasing conditions for extracting leakage current are also illustrated therein, with source nodes 112 coupled to common bit line to received bit line voltage VBL, drain nodes 116 coupled to leakage current extraction node 130 and capacitors 135, and gate nodes 114 coupled to common word line 125 to receive common word line voltage VPP, which turns transistors 111 “off”. Capacitors 135 are coupled between sources 116 and common plate node 140.
The addition to a DRAM memory of a current detector as shown in FIG. 1a or 1b, which requires thousands of dummy sample memory cells, requires a considerable amount of area or space, particularly as the number of bits cells to monitor increases. In addition, it is difficult to utilize the illustrated structure in a practical implementation because leakage current extraction node 130 must be biased at a stable voltage level. In one case, the extraction node 130 must be 0V or close to 0V for extracting leakage current when simulating a memory cell holding the charge of 0V, or so called ‘0’-state. In the opposite case, the extraction node 130 must be VDD or close to VDD for extracting leakage current when simulating memory cells storing data ‘1’. If any disturbance in the voltage or any voltage swing occurs at extraction node 130, these constraints may not be satisfied and the circuit may not operate properly.
Therefore, there is a need for a current monitoring method and circuit that can measure a leakage current that does not use significant area. Further, there is a need for a current monitoring method and circuit that are not affected by the extraction voltage level.